1. Field
Example embodiments relate to a semiconductor package and a method of manufacturing the semiconductor package. More particularly, example embodiments relate to a semiconductor package including semiconductor chips that are stacked on a substrate and electrically connected to the substrate by a plurality of bonding wires and a method of manufacturing the semiconductor package.
2. Description of the Related Art
Generally, semiconductor devices are manufactured by a fabrication (“fab”) process for forming electrical circuits including electrical elements on a semiconductor substrate, e.g., a silicon wafer, an electrical die sorting (EDS) process for inspecting electrical properties of chips formed by the fab process, and a packaging process for sealing the chips with resin, e.g., epoxy, and sorting the chips.
Through the packaging process, the semiconductor device, e.g., a semiconductor chip, is electrically connected to a mounting substrate, and the semiconductor chip is sealed to be protected from the outside. The semiconductor package including the semiconductor chip mounted on the mounting substrate dissipates heat from the semiconductor chip outside through cooling functions thereof.
The semiconductor package may include the mounting substrate and a plurality of semiconductor chips mounted on the mounting substrate. The semiconductor chips may be electrically connected to the mounting substrate by a plurality of bonding wires.
Recently, as the number of input/output signal lines for the semiconductor chip is increased, dimensions of the wiring substrate and line widths between wiring patterns are reduced. In addition, as the number of the stacked semiconductor chips is increased, the height of the semiconductor package is increased.
Especially, because the length and loop height of the bonding wire for electrically connecting a chip pad of the uppermost semiconductor chip to a bonding pad of the mounting substrate are increased, contact failures between adjacent bonding wires or between the bonding wire and the semiconductor chips occur frequently. Accordingly, the semiconductor package may need to have a structure capable of providing a free wire route design without changing the routes and patterns of the existing bonding wires.